In vertical semiconductor devices, current flows between a first side of a semiconductor die to a second side of the semiconductor die, opposite the first side. As an example, current flows from a source of a field effect transistor (FET) at the first side to a drain at the second side. The semiconductor die may be mounted to a carrier, e.g., a lead frame or a direct copper bonded (DCB) substrate, via the second side. In vertical semiconductor devices, a low ohmic contact between a bottom side of the semiconductor device and the carrier as well as a low ohmic current path through the semiconductor device from the first side to the second side are desirable. In semiconductor devices including high current densities during operation, e.g., in low voltage FETs including voltage blocking capabilities below 100 V, any parasitic resistance between the first side and the second side of the device is detrimental. Since a drift zone of low-voltage semiconductor devices is thin, compared to devices including higher voltage blocking capabilities, thin wafer techniques are one way of realizing the devices.
It is desirable to reduce an on-state resistance in a vertical semiconductor device.